1. Field of the Invention
The present invention generally relates to a constant voltage power supply, and, in particular, to a constant voltage power supply supplying power to a load having an operation condition and a standby condition switched to one another.
2. Description of the Related Art
A constant voltage power supply having a constant voltage circuit (Voltage Regulator, referred to as a VR, hereinafter) and supplying power in a stable voltage is used in a cellular phone or the like. Such a constant voltage power supply has a constant voltage circuit (high-speed VR) having a large power (current) consumption in order to improve a PSRR (ripple removal rate) and a load transient responsivity. Therefore, when such a constant voltage power supply is applied to a device such as a cellular phone which has an active mode (operation condition) and a sleep mode (standby condition), useless power (current) consumption is large in the sleep mode in which high PSRR and load transient responsitivy are not needed.
In order to solve such a problem, a constant voltage power supply is considered which has the high-speed VR and also another VR (low-speed VR) having lower PSRR and load transient responsivity but having a smaller power (current) consumption and has a function of switching VRs in accordance with the condition of a load. Although the low-speed VR has the PSRR and load transient responsivity lowered as a result of having the smaller power (current) consumption, there is no problem when the load is in the sleep mode.
A configuration shown in FIG. 1 is considered for configuring a constant voltage power supply having the high-speed VR and low-speed VR.
In order to supply power to a load 3 from a power-source voltage applying terminal 1 stably, a high-speed VR 5a and a low-speed VR 5b are provided. For example, the high-speed VR 5a and low-speed VR 5b have transistors having different sizes but having the same configuration. Specifically, the size of the transistor of the high-speed is such as to have a large current supply capability. The high-speed VR 5a and low-speed VR 5b have input terminals (Vbat) 7a and 7b to which the power-source voltage applying terminal 1 is connected, reference voltage parts (Vref) 9a and 9b, operational amplifiers (OPAMP) 11a and 11b, output transistors (P-channel MOS transistors: DRV) 13a and 13b, voltage-dividing resistors R1, R2 and R3, R4, and output terminals 15a and 15b, respectively.
In the high-speed VR 5a, the output terminal of the operational amplifier 11a is connected to the gate electrode of the output transistor 13a, the reference voltage Vref is applied to the inverted input terminal of the operational amplifier 11a by the reference voltage part 9a, the voltage obtained as a result of the output voltage Vout being divided by the resistors R1 and R2 is applied to the non-inverted input terminal of the operational amplifier 11a, and control is performed such that the voltage obtained as a result of the output voltage Vout being divided by the resistors R1 and R2 is equal to the reference voltage.
The high-speed VR 5a and low-speed VR 5b enclosed by broken lines, respectively, are formed on separate chips, respectively.
The output terminals 15a and 15b of the high-speed VR 5a and low-speed VR 5b are connected to the load 3 through a switching unit 17. The load 3 has an active mode in which the power consumption is tens of mA and a sleep mode in which the power consumption is tens of .mu.A switched to one another. A switching logic circuit (switching LOGIC) 19 which outputs switching signals to the switching unit 17 is connected to the load 3. The switching logic circuit 19 outputs to the switching unit 17 a switching signal "H" when the load 3 is in the active mode but a switching signal "L" when the load 3 is in the sleep mode. The switching unit 17 connects the output terminal 15a of the high-speed VR 5a to the load 3 when having the switching signal "H" input thereto, but connects the output terminal 15b of the low-speed VR 5b to the load 3 when having the switching signal "L" input thereto. Thus, the high-speed VR 5a or low-speed VR 5b is selected in accordance with the condition of the load 3.
Each of the high-speed VR 5a and low-speed VR 5b enters a standby condition when not being selected, and have the power (current) consumption equal to or smaller than 1 .mu.A.
Thus, the high-speed VR 5a is selected when the load 3 is in the active mode, but the low-speed VR 5b is selected when the load 3 is in the sleep mode. Thereby, the power (current) consumption is appropriately controlled.
However, in the configuration shown in FIG. 1, when the high-speed VR 5a, low-speed VR 5b and switching unit 17 are mounted on one chip (semiconductor chip), the two output transistors 13a and 13b need large areas thereon. Further, because the switching unit 17 needs to have a capability of having a current flowing therethrough equivalent to the output transistors 13a and 13b, and thus to have a low resistance, it also needs a large area. Thus, when this configuration is achieved on one chip including the switching unit 17, the chip area is considerably large.